1. Field of the Invention
The present invention relates generally to packaging of electronic components. More particularly, the present invention relates to wafer-level chip-scale packaging of electronic components.
2. Description of Related Art
Generally, a wafer-level chip-scale package is a semiconductor package in which the size of a finished package is similar to or slightly larger than a semiconductor die. After completion of all assembling processes or packaging processes, individual semiconductor packages are separated from a wafer having a plurality of semiconductor dies.
In this wafer-level chip-scale package, a plurality of bond pads formed on the semiconductor die is redistributed through conventional redistribution processes involving a redistribution layer (RDL) into a plurality of metal pads in an area array type. The metal pads are solder wettable surfaces, e.g. copper (Cu), nickel (Ni) or its equivalent. Solder balls are directly fused on the metal pads, which are formed in the area array type by means of the redistribution process. A protective layer, which is thicker than an oxide film (SiO2) (or a nitride film (Si3N4) and TEOS (Tetra Ethyl Ortho Silicate)), is formed at the entire surface of the semiconductor die except at apertures in the protective layer at the metal pads so as to positively protect the surface of the semiconductor die from the external environment and to easily perform the solder ball bumping and fusing process. That is, the protective layer is formed in such a manner that the thickness of the protective layer is thicker than the oxide film, and then the solder balls are bumped and fused on the metal pads, which are open upward through the protective layer prior to solder ball bumping. Since the protective layer is formed on the surface of the oxide layer, the opening size to the metal pads becomes smaller.
More recently, there are occasions in which, after forming the protective layer (hereinafter, referred to as ‘a first protective layer’) on the upper surface of the semiconductor die, metal lines for a variety of passive elements, such as resistors, inductors and capacitors, are further formed on the surface of the first protective layer, in order to implement, for example, Integrated Passive Networks (IPN) functions. The metal lines for the passive elements are connected to semiconductor die directly or indirectly via the RDL metal lines, which are formed at a lower part of the first protective layer. At this time, in order to prevent an electrical interaction between the metal lines for the passive elements and other metal lines, for example the RDL metal lines formed on a lower part of the first protective layer of the semiconductor die, the first protective layer is relatively thickly formed. A second protective layer can be relatively thickly formed at the surface of the first protective layer in order to protect the metal lines for the passive elements. At this time, the metal pads are also open to the outside through the second protective layer.
However, as the exposed region of the first protective layer is covered with the second protective layer, the size of the opening to the metal pads is decreased. That is, since the second protective layer is formed on the top surface of the first protective layer, the opening size formed through the second protective layer to the metal pads becomes much smaller than that formed through the first protective layer to the metal pads. Accordingly, where the overall opening size to the metal pads decreases, the contact area of the solder ball that is fused to the metal pad becomes smaller and the density of electric currents flowing through it becomes larger, thereby deteriorating the reliability of the package. Also, because the opening size to the metal pads becomes smaller, it is necessary for the solder balls to be bumped very precisely on the metal pads, thereby the rate of inferior goods increases and the production yield of the semiconductor package is remarkably decreased.